Logic design knowledge

MIPS Assembly Programming, Single Cycle CPU, Multicycle CPU, Pipelined CPU,

Cache and memory architectures, I/O concepts

The purpose of this course is to teach the basic computer architecture concepts with the

assembly programming and the CPU internals

Computer Organization and Design: The Hardware/Software Interface. Third Edition

Homeworks % 10,

Laboratory work % 25,

Midterm % 30,

Final % 35

Due to academic rules, cheating is strongly prohibited. The penalty for the cheating is

determined by the Izmir University.

Introduction to basic concepts

MIPS: ISA concepts, instruction types

MIPS: Instructions and decisions

MIPS: arrays, procedure calls, system calls,

stack concept.

Single cycle MIPS datapath with control

Multi cycle MIPS datapath with control

Multi cycle MIPS datapath with control

Multi cycle MIPS datapath with control,

Pipelined datapath

Pipelined datapath.

Data and Branch hazards, exceptions.

Data and Branch hazards, exceptions.

Memory and caches.

Interrupts, Interfacing, I/O concepts,

performance issues