EEE102 Logic Design

EEE102 Logic Design

1. Prerequisites	:	none
2. Contents	:	Binary number systems - a review, Boolean algebra and logic gates, AND, NAND, OR, NOR, gate technologies – open collector, tri-state, TTL, ECL, gate level minimisation, Karnaugh diagramme, combinational logic, encoders and decoders, multiplexers, synchronous sequential logic, flipflops, registers and counters, asynchronous sequential logic, clocking.
3. Objectives	:
4. Textbook/ Lecture notes	:	M. Morris Mano, Michael D. Ciletti: “Digital Design”, Upper Saddle River, Pearson Prentice Hall, 2007.
5. Attendance	:	Compulsory attendance for theory lectures is 70% and for laboratory 80%.
6. Grading	:	Laboratory 30% Midterm 30% Final 40%
7. Academic dishonesty	:	Academic dishonesty is related to cheating and plagiarism. Copying in whole or in part others’ assignments, lab works or exams, is considered cheating respectively plagiarism. All parties involved will receive a zero score for the lab, assignment or the exam.